.. _program_listing_file_include_libcaer_devices_dynapse.h: Program Listing for File dynapse.h ================================== |exhale_lsh| :ref:`Return to documentation for file ` (``include/libcaer/devices/dynapse.h``) .. |exhale_lsh| unicode:: U+021B0 .. UPWARDS ARROW WITH TIP LEFTWARDS .. code-block:: cpp #ifndef LIBCAER_DEVICES_DYNAPSE_H_ #define LIBCAER_DEVICES_DYNAPSE_H_ #include "../events/special.h" #include "../events/spike.h" #include "usb.h" #ifdef __cplusplus extern "C" { #endif #define CAER_DEVICE_DYNAPSE 3 #define DYNAPSE_CHIP_DYNAPSE 64 #define DYNAPSE_CONFIG_MUX 0 #define DYNAPSE_CONFIG_AER 1 #define DYNAPSE_CONFIG_CHIP 5 #define DYNAPSE_CONFIG_SYSINFO 6 #define DYNAPSE_CONFIG_USB 9 #define DYNAPSE_CONFIG_CLEAR_CAM 10 #define DYNAPSE_CONFIG_DEFAULT_SRAM 11 #define DYNAPSE_CONFIG_MONITOR_NEU 12 #define DYNAPSE_CONFIG_DEFAULT_SRAM_EMPTY 13 #define DYNAPSE_CONFIG_SRAM 14 #define DYNAPSE_CONFIG_SYNAPSERECONFIG 15 #define DYNAPSE_CONFIG_SPIKEGEN 16 #define DYNAPSE_CONFIG_TAU2_SET 17 #define DYNAPSE_CONFIG_POISSONSPIKEGEN 18 #define DYNAPSE_CONFIG_TAU1_RESET 19 #define DYNAPSE_CONFIG_TAU2_RESET 20 #define DYNAPSE_CONFIG_POISSONSPIKEGEN_RUN 0 #define DYNAPSE_CONFIG_POISSONSPIKEGEN_WRITEADDRESS 1 #define DYNAPSE_CONFIG_POISSONSPIKEGEN_WRITEDATA 2 #define DYNAPSE_CONFIG_POISSONSPIKEGEN_CHIPID 3 #define DYNAPSE_CONFIG_SPIKEGEN_RUN 0 #define DYNAPSE_CONFIG_SPIKEGEN_VARMODE 1 #define DYNAPSE_CONFIG_SPIKEGEN_BASEADDR 2 #define DYNAPSE_CONFIG_SPIKEGEN_STIMCOUNT 3 #define DYNAPSE_CONFIG_SPIKEGEN_ISI 4 #define DYNAPSE_CONFIG_SPIKEGEN_ISIBASE 5 #define DYNAPSE_CONFIG_SPIKEGEN_REPEAT 6 #define DYNAPSE_CONFIG_SYNAPSERECONFIG_RUN 0 #define DYNAPSE_CONFIG_SYNAPSERECONFIG_GLOBALKERNEL 1 #define DYNAPSE_CONFIG_SYNAPSERECONFIG_USESRAMKERNELS 2 #define DYNAPSE_CONFIG_SYNAPSERECONFIG_CHIPSELECT 3 #define DYNAPSE_CONFIG_SYNAPSERECONFIG_SRAMBASEADDR 4 #define DYNAPSE_CONFIG_SRAM_ADDRESS 1 #define DYNAPSE_CONFIG_SRAM_READDATA 2 #define DYNAPSE_CONFIG_SRAM_WRITEDATA 3 #define DYNAPSE_CONFIG_SRAM_RWCOMMAND 4 #define DYNAPSE_CONFIG_SRAM_READ 0 #define DYNAPSE_CONFIG_SRAM_WRITE 1 #define DYNAPSE_CONFIG_SRAM_BURSTMODE 5 #define DYNAPSE_CONFIG_MUX_RUN 0 #define DYNAPSE_CONFIG_MUX_TIMESTAMP_RUN 1 #define DYNAPSE_CONFIG_MUX_TIMESTAMP_RESET 2 #define DYNAPSE_CONFIG_MUX_FORCE_CHIP_BIAS_ENABLE 3 #define DYNAPSE_CONFIG_MUX_DROP_AER_ON_TRANSFER_STALL 4 #define DYNAPSE_CONFIG_MUX_HAS_STATISTICS 10 #define DYNAPSE_CONFIG_MUX_STATISTICS_AER_DROPPED 11 #define DYNAPSE_CONFIG_AER_RUN 3 #define DYNAPSE_CONFIG_AER_ACK_DELAY 4 #define DYNAPSE_CONFIG_AER_ACK_EXTENSION 6 #define DYNAPSE_CONFIG_AER_WAIT_ON_TRANSFER_STALL 8 #define DYNAPSE_CONFIG_AER_EXTERNAL_AER_CONTROL 10 #define DYNAPSE_CONFIG_AER_HAS_STATISTICS 40 #define DYNAPSE_CONFIG_AER_STATISTICS_EVENTS 41 #define DYNAPSE_CONFIG_AER_STATISTICS_EVENTS_DROPPED 45 #define DYNAPSE_CONFIG_CHIP_RUN 0 #define DYNAPSE_CONFIG_CHIP_ID 1 #define DYNAPSE_CONFIG_CHIP_CONTENT 2 #define DYNAPSE_CONFIG_CHIP_REQ_DELAY 3 #define DYNAPSE_CONFIG_CHIP_REQ_EXTENSION 4 #define DYNAPSE_CONFIG_SYSINFO_LOGIC_VERSION 0 #define DYNAPSE_CONFIG_SYSINFO_CHIP_IDENTIFIER 1 #define DYNAPSE_CONFIG_SYSINFO_DEVICE_IS_MASTER 2 #define DYNAPSE_CONFIG_SYSINFO_LOGIC_CLOCK 3 #define DYNAPSE_CONFIG_USB_RUN 0 #define DYNAPSE_CONFIG_USB_EARLY_PACKET_DELAY 1 #define DYNAPSE_CONFIG_SRAM_DIRECTION_POS 0 #define DYNAPSE_CONFIG_SRAM_DIRECTION_NEG 1 #define DYNAPSE_CONFIG_SRAM_DIRECTION_Y_NORTH 0 #define DYNAPSE_CONFIG_SRAM_DIRECTION_Y_SOUTH 1 #define DYNAPSE_CONFIG_SRAM_DIRECTION_X_EAST 0 #define DYNAPSE_CONFIG_SRAM_DIRECTION_X_WEST 1 #define DYNAPSE_X4BOARD_NUMCHIPS 4 #define DYNAPSE_X4BOARD_NEUX 64 #define DYNAPSE_X4BOARD_NEUY 64 #define DYNAPSE_X4BOARD_COREX 4 #define DYNAPSE_X4BOARD_COREY 4 #define DYNAPSE_CONFIG_DYNAPSE_U0 0 #define DYNAPSE_CONFIG_DYNAPSE_U1 1 #define DYNAPSE_CONFIG_DYNAPSE_U2 2 #define DYNAPSE_CONFIG_DYNAPSE_U3 3 #define DYNAPSE_CONFIG_NUMCORES 4 #define DYNAPSE_CONFIG_NUMNEURONS 1024 #define DYNAPSE_CONFIG_NUMNEURONS_CORE 256 #define DYNAPSE_CONFIG_XCHIPSIZE 32 #define DYNAPSE_CONFIG_YCHIPSIZE 32 #define DYNAPSE_CONFIG_NEUCOL 16 #define DYNAPSE_CONFIG_NEUROW 16 #define DYNAPSE_CONFIG_CAMCOL 16 #define DYNAPSE_CONFIG_NUMCAM_NEU 64 #define DYNAPSE_CONFIG_NUMSRAM_NEU 4 #define DYNAPSE_CONFIG_CAMTYPE_F_EXC 3 #define DYNAPSE_CONFIG_CAMTYPE_S_EXC 2 #define DYNAPSE_CONFIG_CAMTYPE_F_INH 1 #define DYNAPSE_CONFIG_CAMTYPE_S_INH 0 #define DYNAPSE_CONFIG_BIAS_C0_PULSE_PWLK_P 0 #define DYNAPSE_CONFIG_BIAS_C0_PS_WEIGHT_INH_S_N 2 #define DYNAPSE_CONFIG_BIAS_C0_PS_WEIGHT_INH_F_N 4 #define DYNAPSE_CONFIG_BIAS_C0_PS_WEIGHT_EXC_S_N 6 #define DYNAPSE_CONFIG_BIAS_C0_PS_WEIGHT_EXC_F_N 8 #define DYNAPSE_CONFIG_BIAS_C0_IF_RFR_N 10 #define DYNAPSE_CONFIG_BIAS_C0_IF_TAU1_N 12 #define DYNAPSE_CONFIG_BIAS_C0_IF_AHTAU_N 14 #define DYNAPSE_CONFIG_BIAS_C0_IF_CASC_N 16 #define DYNAPSE_CONFIG_BIAS_C0_IF_TAU2_N 18 #define DYNAPSE_CONFIG_BIAS_C0_IF_BUF_P 20 #define DYNAPSE_CONFIG_BIAS_C0_IF_AHTHR_N 22 #define DYNAPSE_CONFIG_BIAS_C0_IF_THR_N 24 #define DYNAPSE_CONFIG_BIAS_C0_NPDPIE_THR_S_P 26 #define DYNAPSE_CONFIG_BIAS_C0_NPDPIE_THR_F_P 28 #define DYNAPSE_CONFIG_BIAS_C0_NPDPII_THR_F_P 30 #define DYNAPSE_CONFIG_BIAS_C0_NPDPII_THR_S_P 32 #define DYNAPSE_CONFIG_BIAS_C0_IF_NMDA_N 34 #define DYNAPSE_CONFIG_BIAS_C0_IF_DC_P 36 #define DYNAPSE_CONFIG_BIAS_C0_IF_AHW_P 38 #define DYNAPSE_CONFIG_BIAS_C0_NPDPII_TAU_S_P 40 #define DYNAPSE_CONFIG_BIAS_C0_NPDPII_TAU_F_P 42 #define DYNAPSE_CONFIG_BIAS_C0_NPDPIE_TAU_F_P 44 #define DYNAPSE_CONFIG_BIAS_C0_NPDPIE_TAU_S_P 46 #define DYNAPSE_CONFIG_BIAS_C0_R2R_P 48 #define DYNAPSE_CONFIG_BIAS_C1_PULSE_PWLK_P 1 #define DYNAPSE_CONFIG_BIAS_C1_PS_WEIGHT_INH_S_N 3 #define DYNAPSE_CONFIG_BIAS_C1_PS_WEIGHT_INH_F_N 5 #define DYNAPSE_CONFIG_BIAS_C1_PS_WEIGHT_EXC_S_N 7 #define DYNAPSE_CONFIG_BIAS_C1_PS_WEIGHT_EXC_F_N 9 #define DYNAPSE_CONFIG_BIAS_C1_IF_RFR_N 11 #define DYNAPSE_CONFIG_BIAS_C1_IF_TAU1_N 13 #define DYNAPSE_CONFIG_BIAS_C1_IF_AHTAU_N 15 #define DYNAPSE_CONFIG_BIAS_C1_IF_CASC_N 17 #define DYNAPSE_CONFIG_BIAS_C1_IF_TAU2_N 19 #define DYNAPSE_CONFIG_BIAS_C1_IF_BUF_P 21 #define DYNAPSE_CONFIG_BIAS_C1_IF_AHTHR_N 23 #define DYNAPSE_CONFIG_BIAS_C1_IF_THR_N 25 #define DYNAPSE_CONFIG_BIAS_C1_NPDPIE_THR_S_P 27 #define DYNAPSE_CONFIG_BIAS_C1_NPDPIE_THR_F_P 29 #define DYNAPSE_CONFIG_BIAS_C1_NPDPII_THR_F_P 31 #define DYNAPSE_CONFIG_BIAS_C1_NPDPII_THR_S_P 33 #define DYNAPSE_CONFIG_BIAS_C1_IF_NMDA_N 35 #define DYNAPSE_CONFIG_BIAS_C1_IF_DC_P 37 #define DYNAPSE_CONFIG_BIAS_C1_IF_AHW_P 39 #define DYNAPSE_CONFIG_BIAS_C1_NPDPII_TAU_S_P 41 #define DYNAPSE_CONFIG_BIAS_C1_NPDPII_TAU_F_P 43 #define DYNAPSE_CONFIG_BIAS_C1_NPDPIE_TAU_F_P 45 #define DYNAPSE_CONFIG_BIAS_C1_NPDPIE_TAU_S_P 47 #define DYNAPSE_CONFIG_BIAS_C1_R2R_P 49 #define DYNAPSE_CONFIG_BIAS_U_BUFFER 50 #define DYNAPSE_CONFIG_BIAS_U_SSP 51 #define DYNAPSE_CONFIG_BIAS_U_SSN 52 #define DYNAPSE_CONFIG_BIAS_C2_PULSE_PWLK_P 64 #define DYNAPSE_CONFIG_BIAS_C2_PS_WEIGHT_INH_S_N 66 #define DYNAPSE_CONFIG_BIAS_C2_PS_WEIGHT_INH_F_N 68 #define DYNAPSE_CONFIG_BIAS_C2_PS_WEIGHT_EXC_S_N 70 #define DYNAPSE_CONFIG_BIAS_C2_PS_WEIGHT_EXC_F_N 72 #define DYNAPSE_CONFIG_BIAS_C2_IF_RFR_N 74 #define DYNAPSE_CONFIG_BIAS_C2_IF_TAU1_N 76 #define DYNAPSE_CONFIG_BIAS_C2_IF_AHTAU_N 78 #define DYNAPSE_CONFIG_BIAS_C2_IF_CASC_N 80 #define DYNAPSE_CONFIG_BIAS_C2_IF_TAU2_N 82 #define DYNAPSE_CONFIG_BIAS_C2_IF_BUF_P 84 #define DYNAPSE_CONFIG_BIAS_C2_IF_AHTHR_N 86 #define DYNAPSE_CONFIG_BIAS_C2_IF_THR_N 88 #define DYNAPSE_CONFIG_BIAS_C2_NPDPIE_THR_S_P 90 #define DYNAPSE_CONFIG_BIAS_C2_NPDPIE_THR_F_P 92 #define DYNAPSE_CONFIG_BIAS_C2_NPDPII_THR_F_P 94 #define DYNAPSE_CONFIG_BIAS_C2_NPDPII_THR_S_P 96 #define DYNAPSE_CONFIG_BIAS_C2_IF_NMDA_N 98 #define DYNAPSE_CONFIG_BIAS_C2_IF_DC_P 100 #define DYNAPSE_CONFIG_BIAS_C2_IF_AHW_P 102 #define DYNAPSE_CONFIG_BIAS_C2_NPDPII_TAU_S_P 104 #define DYNAPSE_CONFIG_BIAS_C2_NPDPII_TAU_F_P 106 #define DYNAPSE_CONFIG_BIAS_C2_NPDPIE_TAU_F_P 108 #define DYNAPSE_CONFIG_BIAS_C2_NPDPIE_TAU_S_P 110 #define DYNAPSE_CONFIG_BIAS_C2_R2R_P 112 #define DYNAPSE_CONFIG_BIAS_C3_PULSE_PWLK_P 65 #define DYNAPSE_CONFIG_BIAS_C3_PS_WEIGHT_INH_S_N 67 #define DYNAPSE_CONFIG_BIAS_C3_PS_WEIGHT_INH_F_N 69 #define DYNAPSE_CONFIG_BIAS_C3_PS_WEIGHT_EXC_S_N 71 #define DYNAPSE_CONFIG_BIAS_C3_PS_WEIGHT_EXC_F_N 73 #define DYNAPSE_CONFIG_BIAS_C3_IF_RFR_N 75 #define DYNAPSE_CONFIG_BIAS_C3_IF_TAU1_N 77 #define DYNAPSE_CONFIG_BIAS_C3_IF_AHTAU_N 79 #define DYNAPSE_CONFIG_BIAS_C3_IF_CASC_N 81 #define DYNAPSE_CONFIG_BIAS_C3_IF_TAU2_N 83 #define DYNAPSE_CONFIG_BIAS_C3_IF_BUF_P 85 #define DYNAPSE_CONFIG_BIAS_C3_IF_AHTHR_N 87 #define DYNAPSE_CONFIG_BIAS_C3_IF_THR_N 89 #define DYNAPSE_CONFIG_BIAS_C3_NPDPIE_THR_S_P 91 #define DYNAPSE_CONFIG_BIAS_C3_NPDPIE_THR_F_P 93 #define DYNAPSE_CONFIG_BIAS_C3_NPDPII_THR_F_P 95 #define DYNAPSE_CONFIG_BIAS_C3_NPDPII_THR_S_P 97 #define DYNAPSE_CONFIG_BIAS_C3_IF_NMDA_N 99 #define DYNAPSE_CONFIG_BIAS_C3_IF_DC_P 101 #define DYNAPSE_CONFIG_BIAS_C3_IF_AHW_P 103 #define DYNAPSE_CONFIG_BIAS_C3_NPDPII_TAU_S_P 105 #define DYNAPSE_CONFIG_BIAS_C3_NPDPII_TAU_F_P 107 #define DYNAPSE_CONFIG_BIAS_C3_NPDPIE_TAU_F_P 109 #define DYNAPSE_CONFIG_BIAS_C3_NPDPIE_TAU_S_P 111 #define DYNAPSE_CONFIG_BIAS_C3_R2R_P 113 #define DYNAPSE_CONFIG_BIAS_D_BUFFER 114 #define DYNAPSE_CONFIG_BIAS_D_SSP 115 #define DYNAPSE_CONFIG_BIAS_D_SSN 116 struct caer_dynapse_info { int16_t deviceID; char deviceSerialNumber[8 + 1]; uint8_t deviceUSBBusNumber; uint8_t deviceUSBDeviceAddress; char *deviceString; int16_t logicVersion; bool deviceIsMaster; int16_t logicClock; int16_t chipID; bool aerHasStatistics; bool muxHasStatistics; }; LIBRARY_PUBLIC_VISIBILITY struct caer_dynapse_info caerDynapseInfoGet(caerDeviceHandle handle); struct caer_bias_dynapse { uint8_t biasAddress; uint8_t coarseValue; uint8_t fineValue; bool enabled; bool sexN; bool typeNormal; bool biasHigh; }; LIBRARY_PUBLIC_VISIBILITY uint32_t caerBiasDynapseGenerate(const struct caer_bias_dynapse dynapseBias); LIBRARY_PUBLIC_VISIBILITY struct caer_bias_dynapse caerBiasDynapseParse(const uint32_t dynapseBias); LIBRARY_PUBLIC_VISIBILITY bool caerDynapseWriteSramWords( caerDeviceHandle handle, const uint16_t *data, uint32_t baseAddr, size_t numWords); LIBRARY_PUBLIC_VISIBILITY bool caerDynapseWritePoissonSpikeRate( caerDeviceHandle handle, uint16_t neuronAddr, float rateHz); DEPRECATED_FUNCTION("Replaced by caerDynapseWriteSramN(), which has an improved interface.") LIBRARY_PUBLIC_VISIBILITY bool caerDynapseWriteSram(caerDeviceHandle handle, uint8_t coreId, uint8_t neuronAddrCore, uint8_t virtualCoreId, bool sx, uint8_t dx, bool sy, uint8_t dy, uint8_t sramId, uint8_t destinationCore); LIBRARY_PUBLIC_VISIBILITY bool caerDynapseWriteSramN(caerDeviceHandle handle, uint16_t neuronAddr, uint8_t sramId, uint8_t virtualCoreId, bool sx, uint8_t dx, bool sy, uint8_t dy, uint8_t destinationCore); LIBRARY_PUBLIC_VISIBILITY bool caerDynapseWriteCam( caerDeviceHandle handle, uint16_t inputNeuronAddr, uint16_t neuronAddr, uint8_t camId, uint8_t synapseType); LIBRARY_PUBLIC_VISIBILITY bool caerDynapseSendDataToUSB( caerDeviceHandle handle, const uint32_t *data, size_t numConfig); LIBRARY_PUBLIC_VISIBILITY uint32_t caerDynapseGenerateCamBits( uint16_t inputNeuronAddr, uint16_t neuronAddr, uint8_t camId, uint8_t synapseType); LIBRARY_PUBLIC_VISIBILITY uint32_t caerDynapseGenerateSramBits(uint16_t neuronAddr, uint8_t sramId, uint8_t virtualCoreId, bool sx, uint8_t dx, bool sy, uint8_t dy, uint8_t destinationCore); LIBRARY_PUBLIC_VISIBILITY uint16_t caerDynapseCoreXYToNeuronId(uint8_t coreId, uint8_t columnX, uint8_t rowY); LIBRARY_PUBLIC_VISIBILITY uint16_t caerDynapseCoreAddrToNeuronId(uint8_t coreId, uint8_t neuronAddrCore); LIBRARY_PUBLIC_VISIBILITY uint16_t caerDynapseSpikeEventGetX(caerSpikeEventConst event); LIBRARY_PUBLIC_VISIBILITY uint16_t caerDynapseSpikeEventGetY(caerSpikeEventConst event); LIBRARY_PUBLIC_VISIBILITY struct caer_spike_event caerDynapseSpikeEventFromXY(uint16_t x, uint16_t y); #ifdef __cplusplus } #endif #endif /* LIBCAER_DEVICES_DYNAPSE_H_ */